/* lteenb configuration file version 2022-02-14 * Copyright (C) 2019-2022 Amarisoft * NR SA FDD or TDD cell */ #define NR_TDD 1 // Values: 0 (NR FDD), 1(NR TDD) #define FR2 0 // Values: 0 (FR1), 1 (FR2) #define NR_TDD_CONFIG 2 // Values: FR1: 1, 2, 3, 4 (compatible with LTE TDD config 2) FR2: 10 #define N_ANTENNA_DL 2 // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4) #define N_ANTENNA_UL 1 // Values: 1, 2, 4 #define NR_BANDWIDTH 20 // NR cell bandwidth #define NR_LONG_PUCCH_FORMAT 2 // Values: 2, 3, 4 /* define to 1 to enable periodic SRS with N_ANTENNA_UL ports. Uplink SU-MIMO is also enabled if N_ANTENNA_UL >= 2. Not all UEs support uplink SU-MIMO. */ #define USE_SRS 0 { //log_options: "all.level=debug,all.max_size=1", log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,ngap.level=debug,ngap.max_size=1,xnap.level=debug,xnap.max_size=1,rrc.level=debug,rrc.max_size=1", log_filename: "/tmp/gnb0.log", /* Enable remote API and Web interface */ com_addr: "0.0.0.0:9001", rf_driver: { name: "sdr", /* list of devices. 'dev0' is always the master. */ #if N_ANTENNA_DL >= 4 args: "dev0=/dev/sdr0,dev1=/dev/sdr1", #else args: "dev0=/dev/sdr0", #endif /* TDD: force the RX antenna on the RX connector */ rx_antenna: "rx", /* synchronisation source: none, internal, gps, external (default = none) */ // sync: "gps", }, tx_gain: 90.0, /* TX gain (in dB) */ rx_gain: 60.0, /* RX gain (in dB) */ amf_list: [ { /* address of AMF for NGAP connection. Must be modified if the AMF runs on a different host. */ amf_addr: "127.0.1.100", }, ], /* GTP bind address (=address of the ethernet interface connected to the AMF). Must be modified if the AMF runs on a different host. */ gtp_addr: "127.0.1.1", gnb_id_bits: 28, gnb_id: 0x12345, en_dc_support: true, rf_ports: [ { #if FR2 /* an external frequency translator must be used for FR2 */ rf_dl_freq: 3500, /* MHz */ rf_ul_freq: 3500, /* MHz */ #endif }, ], /* list of cells */ cell_list: [], nr_cell_list: [ { rf_port: 0, cell_id: 0x01, #if NR_TDD == 1 #if FR2 band: 257, dl_nr_arfcn: 2079167, /* 28000.08 MHz */ subcarrier_spacing: 120, /* kHz */ ssb_pos_bitmap: "0100000000000000000000000000000000000000000000000000000000000000", /* uncomment to have a higher per-UE bitrate at the expense of higher gNB real time constraints. */ // rx_to_tx_latency: 10, /* slots */ #else band: 78, dl_nr_arfcn: 632628, /* 3489.42 MHz */ subcarrier_spacing: 30, /* kHz */ ssb_pos_bitmap: "10000000", #endif #else band: 7, dl_nr_arfcn: 536000, /* 2680 MHz */ ssb_subcarrier_spacing: 15, subcarrier_spacing: 30, /* kHz */ ssb_pos_bitmap: "1000", #endif }, ], /* nr_cell_list */ nr_cell_default: { bandwidth: NR_BANDWIDTH, /* MHz */ n_antenna_dl: N_ANTENNA_DL, n_antenna_ul: N_ANTENNA_UL, /* force the timing TA offset (optional) */ // n_timing_advance_offset: 39936, /* subframe offset to align with the LTE TDD pattern (optional) */ // subframe_offset: 2, #if NR_TDD == 1 tdd_ul_dl_config: { #if NR_TDD_CONFIG == 1 pattern1: { period: 5, /* in ms */ dl_slots: 7, dl_symbols: /* 6 */ 2, ul_slots: 2, ul_symbols: 2, }, #elif NR_TDD_CONFIG == 2 pattern1: { period: 5, /* in ms */ dl_slots: 7, dl_symbols: 6, ul_slots: 2, ul_symbols: 4, }, #elif NR_TDD_CONFIG == 3 pattern1: { period: 5, /* in ms */ dl_slots: 6, dl_symbols: 2, ul_slots: 3, ul_symbols: 2, }, #elif NR_TDD_CONFIG == 4 pattern1: { period: 3, /* in ms */ dl_slots: 3, dl_symbols: 6, ul_symbols: 4, ul_slots: 2, }, pattern2: { period: 2, /* in ms */ dl_slots: 4, dl_symbols: 0, ul_symbols: 0, ul_slots: 0, }, #elif NR_TDD_CONFIG == 10 /* only for FR2 */ pattern1: { period: 0.625, /* in ms */ dl_slots: 3, dl_symbols: 10, ul_slots: 1, ul_symbols: 2, }, #endif }, #endif ssb_period: 20, /* in ms */ n_id_cell: 500, plmn_list: [ { tac: 100, plmn: "00101", reserved: false, nssai: [ { sst: 1, }, /*{ sst: 2, }, { sst: 3, sd: 50, },*/ ], }, ], /*sib_sched_list: [ { filename: "sib2_nr.asn", si_periodicity: 16, }, { filename: "sib3_nr.asn", si_periodicity: 16, }, { filename: "sib4_nr.asn", si_periodicity: 32, }, ], sib9: { si_periodicity: 32 },*/ si_window_length: 40, cell_barred: false, intra_freq_reselection: true, q_rx_lev_min: -70, q_qual_min: -20, //p_max: 10, /* dBm */ root_sequence_index: 1, /* PRACH root sequence index */ /* Scheduling request period (slots). */ sr_period: 40, dmrs_type_a_pos: 2, /* to limit the number of HARQ feedback in UL, use pdsch_harq_ack_max; allows to workaround issues with SM-G977N for example */ //pdsch_harq_ack_max: 2, prach: { #if NR_TDD == 1 #if FR2 prach_config_index: 149, /* format C0, every 4 frames */ msg1_subcarrier_spacing: 120, /* kHz */ #else #if NR_TDD_CONFIG == 4 prach_config_index: 156, /* format B4, subframe 2 */ #else prach_config_index: 160, /* format B4, subframe 9 */ #endif msg1_subcarrier_spacing: 30, /* kHz */ #endif #else prach_config_index: 16, /* subframe 1 every frame */ #endif msg1_fdm: 1, msg1_frequency_start: -1, zero_correlation_zone_config: 15, preamble_received_target_power: -110, /* in dBm */ preamble_trans_max: 7, power_ramping_step: 4, /* in dB */ #if FR2 ra_response_window: 40, /* in slots */ #else ra_response_window: 20, /* in slots */ #endif restricted_set_config: "unrestricted_set", ra_contention_resolution_timer: 64, /* in ms */ ssb_per_prach_occasion: 1, cb_preambles_per_ssb: 8, }, pdcch: { search_space0_index: 0, dedicated_coreset: { rb_start: -1, /* -1 to have the maximum bandwidth */ l_crb: -1, /* -1 means all the bandwidth */ duration: 0, /* 0 means to automatically set it from the coreset bandwidth */ precoder_granularity: "sameAsREG_bundle", }, css: { n_candidates: [ 0, 0, 4, 0, 0 ], }, rar_al_index: 2, si_al_index: 2, uss: { n_candidates: [ 0, 4, 0, 0, 0 ], dci_0_1_and_1_1: true, }, al_index: 1, }, #if FR2 k_min: 8, #endif pdsch: { mapping_type: "typeA", dmrs_add_pos: 1, dmrs_type: 1, dmrs_max_len: 1, /* k0 delay in slots from DCI to PDSCH: automatic setting */ /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */ mcs_table: "qam256", rar_mcs: 2, si_mcs: 6, /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed * based on DL channel quality estimation */ /* mcs: 24, */ }, csi_rs: { nzp_csi_rs_resource: [ { csi_rs_id: 0, #if N_ANTENNA_DL == 1 n_ports: 1, frequency_domain_allocation: "row2", bitmap: "100000000000", cdm_type: "no_cdm", #elif N_ANTENNA_DL == 2 n_ports: 2, frequency_domain_allocation: "other", bitmap: "100000", cdm_type: "fd_cdm2", #elif N_ANTENNA_DL == 4 n_ports: 4, frequency_domain_allocation: "row4", bitmap: "100", cdm_type: "fd_cdm2", #elif N_ANTENNA_DL == 8 n_ports: 8, frequency_domain_allocation: "other", bitmap: "110011", cdm_type: "fd_cdm2", #else #error unsupported number of DL antennas #endif density: 1, first_symb: 4, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ power_control_offset: 0, /* dB */ power_control_offset_ss: 0, /* dB */ period: 80, offset: 1, /* != 0 to avoid collision with SSB */ qcl_info_periodic_csi_rs: 0, }, #if FR2 == 0 #define USE_TRS #endif #ifdef USE_TRS /* TRS : period of 40 ms, slots 1 & 2, symbols 4 and 8 */ { csi_rs_id: 1, n_ports: 1, frequency_domain_allocation: "row1", bitmap: "0001", cdm_type: "no_cdm", density: 3, first_symb: 4, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ power_control_offset: 0, /* dB */ power_control_offset_ss: 0, /* dB */ period: 40, offset: 11, qcl_info_periodic_csi_rs: 0, }, { csi_rs_id: 2, n_ports: 1, frequency_domain_allocation: "row1", bitmap: "0001", cdm_type: "no_cdm", density: 3, first_symb: 8, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ power_control_offset: 0, /* dB */ power_control_offset_ss: 0, /* dB */ period: 40, offset: 11, qcl_info_periodic_csi_rs: 0, }, { csi_rs_id: 3, n_ports: 1, frequency_domain_allocation: "row1", bitmap: "0001", cdm_type: "no_cdm", density: 3, first_symb: 4, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ power_control_offset: 0, /* dB */ power_control_offset_ss: 0, /* dB */ period: 40, offset: 12, qcl_info_periodic_csi_rs: 0, }, { csi_rs_id: 4, n_ports: 1, frequency_domain_allocation: "row1", bitmap: "0001", cdm_type: "no_cdm", density: 3, first_symb: 8, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ power_control_offset: 0, /* dB */ power_control_offset_ss: 0, /* dB */ period: 40, offset: 12, qcl_info_periodic_csi_rs: 0, }, #endif ], nzp_csi_rs_resource_set: [ { csi_rs_set_id: 0, nzp_csi_rs_resources: [ 0 ], repetition: false, }, #ifdef USE_TRS { csi_rs_set_id: 1, nzp_csi_rs_resources: [ 1, 2, 3, 4 ], repetition: false, trs_info: true, }, #endif ], csi_im_resource: [ { csi_im_id: 0, pattern: 1, subcarrier_location: 8, symbol_location: 8, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ period: 80, offset: 1, /* != 0 to avoid collision with SSB */ }, ], csi_im_resource_set: [ { csi_im_set_id: 0, csi_im_resources: [ 0 ], } ], /* ZP CSI-RS to set the CSI-IM REs to zero */ zp_csi_rs_resource: [ { csi_rs_id: 0, frequency_domain_allocation: "row4", bitmap: "100", n_ports: 4, cdm_type: "fd_cdm2", first_symb: 8, density: 1, rb_start: 0, l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */ period: 80, offset: 1, }, ], p_zp_csi_rs_resource_set: [ { zp_csi_rs_resources: [ 0 ], }, ], csi_resource_config: [ { csi_rsc_config_id: 0, nzp_csi_rs_resource_set_list: [ 0 ], resource_type: "periodic", }, { csi_rsc_config_id: 1, csi_im_resource_set_list: [ 0 ], resource_type: "periodic", }, #ifdef USE_TRS { csi_rsc_config_id: 2, nzp_csi_rs_resource_set_list: [ 1 ], resource_type: "periodic", }, #endif ], csi_report_config: [ { resources_for_channel_measurement: 0, csi_im_resources_for_interference: 1, report_config_type: "periodic", period: 80, report_quantity: "CRI_RI_PMI_CQI", #if N_ANTENNA_DL > 1 codebook_config: { codebook_type: "type1", sub_type: "typeI_SinglePanel", #if N_ANTENNA_DL == 2 #elif N_ANTENNA_DL == 4 n1: 2, n2: 1, codebook_mode: 1, #elif N_ANTENNA_DL == 8 n1: 4, n2: 1, codebook_mode: 1, #endif }, #endif cqi_table: 2, subband_size: "value1", }, ], }, pucch: { pucch_group_hopping: "neither", hopping_id: -1, /* -1 = n_cell_id */ p0_nominal: -90, dpc_snr_target: 10, #if 0 pucch0: { initial_cyclic_shift: 1, n_symb: 1, }, #else pucch1: { n_cs: 3, n_occ: 3, freq_hopping: true, #if USE_SRS && NR_TDD == 0 n_symb: 13, #endif }, #endif #if NR_LONG_PUCCH_FORMAT == 2 pucch2: { n_symb: 2, n_prb: 1, freq_hopping: true, simultaneous_harq_ack_csi: false, max_code_rate: 0.25, }, #elif NR_LONG_PUCCH_FORMAT == 3 pucch3: { bpsk: false, additional_dmrs: false, freq_hopping: true, n_prb: 1, simultaneous_harq_ack_csi: true, max_code_rate: 0.25, }, #elif NR_LONG_PUCCH_FORMAT == 4 pucch4: { occ_len: 4, bpsk: false, additional_dmrs: false, freq_hopping: true, simultaneous_harq_ack_csi: true, max_code_rate: 0.25, }, #endif }, #if USE_SRS srs: { #if NR_TDD #if NR_TDD_CONFIG == 1 || NR_TDD_CONFIG == 2 srs_symbols: [ 0, 0, 0, 0, 0, 0, 0, 2, 0, 0 ], #elif NR_TDD_CONFIG == 3 srs_symbols: [ 0, 0, 0, 0, 0, 0, 2, 0, 0, 0 ], #elif NR_TDD_CONFIG == 4 srs_symbols: [ 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 ], #elif NR_TDD_CONFIG == 10 srs_symbols: [ 0, 0, 0, 2, 0 ], #endif #else srs_symbols: [ 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 ], #endif srs_resource: [ { srs_resource_id: 0, n_ports: N_ANTENNA_UL, resource_type: "periodic", period: 80, /* in slots */ } ], srs_resource_set: [ { srs_resource_id_list: [ 0 ], }, ], }, #endif pusch: { mapping_type: "typeA", n_symb: 14, dmrs_add_pos: 1, dmrs_type: 1, dmrs_max_len: 1, tf_precoding: false, mcs_table: "qam256", /* without transform precoding */ mcs_table_tp: "qam256", /* with transform precoding */ ldpc_max_its: 5, /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */ p0_nominal_with_grant: -84, msg3_mcs: 4, msg3_delta_power: 0, /* in dB */ beta_offset_ack_index: 9, dpc_snr_target: 22, #if USE_SRS max_rank: N_ANTENNA_UL, #endif /* if defined, force the PUSCH MCS for all UEs. Otherwise it is computed from the last received PUSCH. */ /* mcs: 16, */ }, /* MAC configuration */ mac_config: { msg3_max_harq_tx: 5, ul_max_harq_tx: 5, /* max number of HARQ transmissions for uplink */ dl_max_harq_tx: 5, /* max number of HARQ transmissions for downlink */ ul_max_consecutive_retx: 30, /* disconnect UE if reached */ dl_max_consecutive_retx: 30, /* disconnect UE if reached */ periodic_bsr_timer: 20, retx_bsr_timer: 320, periodic_phr_timer: 500, prohibit_phr_timer: 200, phr_tx_power_factor_change: "dB3", sr_prohibit_timer: 0, /* in ms, 0 to disable the timer */ sr_trans_max: 64, }, cipher_algo_pref: [], integ_algo_pref: [2, 1], inactivity_timer: 10000, drb_config: "drb_nr.cfg", }, }