/* lteenb configuration file version 2022-03-18
 * Copyright (C) 2019-2022 Amarisoft
 * NR SA 2CC FDD or TDD cell */


#define NR_TDD_CC1           0  // Values: 0 (NR FDD), 1(NR TDD)
#define NR_TDD_CC2           1  // Values: 0 (NR FDD), 1(NR TDD)
#define NR_TDD_CONFIG        2  // Values: 1, 2, 3 or 4 (compatible with LTE TDD config 2)
#define N_ANTENNA_DL         1  // Values: 1 (SISO), 2 (MIMO 2x2), 4 (MIMO 4x4)
#define N_ANTENNA_UL         1  // Values: 1 (SISO), 2 (diversity 2RX), 4 (diversity 4RX)
#define NR_BANDWIDTH_CC1     20 // NR cell bandwidth
#define NR_BANDWIDTH_CC2     20 // NR cell bandwidth 
#define NR_LONG_PUCCH_FORMAT 2  // Values: 2, 3, 4

{
  log_options: "all.level=debug,all.max_size=1",
//  log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,ngap.level=debug,ngap.max_size=1,xnap.level=debug,xnap.max_size=1,rrc.level=debug,rrc.max_size=1",

  log_filename: "/tmp/gnb0.log",

  /* Enable remote API and Web interface */
  com_addr: "0.0.0.0:9001",

  rf_driver: {
        name: "sdr",

        /* list of devices. 'dev0' is always the master. */
#if N_ANTENNA_DL >= 4
        args: "dev0=/dev/sdr0,dev1=/dev/sdr1,dev2=/dev/sdr2,dev3=/dev/sdr3",
#else
        args: "dev0=/dev/sdr0,dev1=/dev/sdr1",
#endif
        /* TDD: force the RX antenna on the RX connector */
        rx_antenna: "rx",

        /* synchronisation source: none, internal, gps, external (default = none) */
        // sync: "gps",
  },
  tx_gain: 90.0, /* TX gain (in dB) */
  rx_gain: 60.0, /* RX gain (in dB) */


  amf_list: [
    {
      /* address of AMF for NGAP connection. Must be modified if the AMF runs on a different host. */
      amf_addr: "127.0.1.100",
    },
  ],
  /* GTP bind address (=address of the ethernet interface connected to
     the AMF). Must be modified if the AMF runs on a different host. */
  gtp_addr: "127.0.1.1",

  gnb_id_bits: 28,
  gnb_id: 0x12345,

  en_dc_support: true,

  /* list of cells */
  cell_list: [],

  nr_cell_list: [
  {
    rf_port: 0,
    cell_id: 0x01,
    n_id_cell: 500,
    scell_list : [
      {cell_id: 2},
    ],
	
    bandwidth: NR_BANDWIDTH_CC1, /* MHz */
    n_antenna_dl: N_ANTENNA_DL,
    n_antenna_ul: N_ANTENNA_UL,

#if NR_TDD_CC1 == 1
    band: 78,
    dl_nr_arfcn: 621300,
    subcarrier_spacing: 30,
#else
    band: 5,
    dl_nr_arfcn: 176300,
    subcarrier_spacing: 15, /* kHz */
#endif


    prach: {
#if NR_TDD_CC1 == 1
#if NR_TDD_CONFIG == 4
      prach_config_index: 156, /* format B4, subframe 2 */
#else
      prach_config_index: 160, /* format B4, subframe 9 */
#endif
      msg1_subcarrier_spacing: 30, /* kHz */
#else
      prach_config_index: 16, /* subframe 1 every frame */
#endif
      msg1_fdm: 1,
      msg1_frequency_start: -1,
      zero_correlation_zone_config: 15,
      preamble_received_target_power: -110, /* in dBm */
      preamble_trans_max: 7,
      power_ramping_step: 4, /* in dB */
#if NR_TDD_CC1 == 1
      ra_response_window: 20, /* in slots */
#else
      ra_response_window: 10, /* in slots */
#endif
      restricted_set_config: "unrestricted_set",
      ra_contention_resolution_timer: 64, /* in ms */
      ssb_per_prach_occasion: 1,
      cb_preambles_per_ssb: 8,
    },

#if NR_TDD_CC1 == 1
    tdd_ul_dl_config: {
      pattern1: {
#if NR_TDD_CONFIG == 1
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: /* 6 */ 2,
        ul_slots: 2,
        ul_symbols: 0,
#elif NR_TDD_CONFIG == 2
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: 6,
        ul_slots: 2,
        ul_symbols: 4,
#elif NR_TDD_CONFIG == 3
        period: 5, /* in ms */
        dl_slots: 6,
        dl_symbols: 2,
        ul_slots: 3,
        ul_symbols: 0,
#elif NR_TDD_CONFIG == 4
        period: 3, /* in ms */
        dl_slots: 3,
        dl_symbols: 6,
        ul_symbols: 4,
        ul_slots: 2,
      },
      pattern2: {
        period: 2, /* in ms */
        dl_slots: 4,
        dl_symbols: 0,
        ul_symbols: 0,
        ul_slots: 0,
#endif
      },
    },
    ssb_pos_bitmap: "10000000",
#else
    ssb_pos_bitmap: "1000",
#endif

  },
  {
    rf_port: 1,
    cell_id: 0x02,
    n_id_cell: 501,
    scell_list : [
      {cell_id: 1},
    ],

    bandwidth: NR_BANDWIDTH_CC2, /* MHz */
    n_antenna_dl: N_ANTENNA_DL,
    n_antenna_ul: N_ANTENNA_UL,
	
#if NR_TDD_CC2 == 1
    band: 78,
    dl_nr_arfcn: 627300,
    subcarrier_spacing : 30,
#else
    band: 5,
    dl_nr_arfcn: 178000,   
    subcarrier_spacing : 15,  
#endif

    prach: {
#if NR_TDD_CC2 == 1
#if NR_TDD_CONFIG == 4
      prach_config_index: 156, /* format B4, subframe 2 */
#else
      prach_config_index: 160, /* format B4, subframe 9 */
#endif
      msg1_subcarrier_spacing: 30, /* kHz */
#else
      prach_config_index: 16, /* subframe 1 every frame */
#endif
      msg1_fdm: 1,
      msg1_frequency_start: -1,
      zero_correlation_zone_config: 15,
      preamble_received_target_power: -110, /* in dBm */
      preamble_trans_max: 7,
      power_ramping_step: 4, /* in dB */
#if NR_TDD_CC2 == 1
      ra_response_window: 20, /* in slots */
#else
      ra_response_window: 10, /* in slots */
#endif
      restricted_set_config: "unrestricted_set",
      ra_contention_resolution_timer: 64, /* in ms */
      ssb_per_prach_occasion: 1,
      cb_preambles_per_ssb: 8,
    },

#if NR_TDD_CC2 == 1
    tdd_ul_dl_config: {
      pattern1: {
#if NR_TDD_CONFIG == 1
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: /* 6 */ 2,
        ul_slots: 2,
        ul_symbols: 0,
#elif NR_TDD_CONFIG == 2
        period: 5, /* in ms */
        dl_slots: 7,
        dl_symbols: 6,
        ul_slots: 2,
        ul_symbols: 4,
#elif NR_TDD_CONFIG == 3
        period: 5, /* in ms */
        dl_slots: 6,
        dl_symbols: 2,
        ul_slots: 3,
        ul_symbols: 0,
#elif NR_TDD_CONFIG == 4
        period: 3, /* in ms */
        dl_slots: 3,
        dl_symbols: 6,
        ul_symbols: 4,
        ul_slots: 2,
      },
      pattern2: {
        period: 2, /* in ms */
        dl_slots: 4,
        dl_symbols: 0,
        ul_symbols: 0,
        ul_slots: 0,
#endif
      },
    },
    ssb_pos_bitmap: "10000000",
#else
    ssb_pos_bitmap: "1000",
#endif

  },
  ], /* nr_cell_list */

  nr_cell_default: {

    /* force the timing TA offset (optional) */
//    n_timing_advance_offset: 39936,


    ssb_period: 20, /* in ms */

    plmn_list: [ {
      tac: 100,
      plmn: "00101",
      reserved: false,
      },
    ],

    /*sib_sched_list: [
      {
        filename: "sib2_nr.asn",
        si_periodicity: 16,
      },
      {
        filename: "sib3_nr.asn",
        si_periodicity: 16,
      },
      {
        filename: "sib4_nr.asn",
        si_periodicity: 32,
      },
    ],
    sib9: {
      si_periodicity: 32
    },*/
    si_window_length: 40,

    cell_barred: false,
    intra_freq_reselection: true,
    q_rx_lev_min: -70,
    q_qual_min: -20,
    //p_max: 10, /* dBm */

    root_sequence_index: 1, /* PRACH root sequence index */

    /* Scheduling request period (slots). */
    sr_period: 40,

    dmrs_type_a_pos: 2,

    /* to limit the number of HARQ feedback in UL, use pdsch_harq_ack_max;
       allows to workaround issues with SM-G977N for example */
    //pdsch_harq_ack_max: 2,


    pdcch: {
      n_rb_coreset0: 48,
      n_symb_coreset0: 1,
      search_space0_index: 0,

      rb_start: -1, /* -1 to have the maximum bandwidth */
      l_crb: -1, /* -1 means all the bandwidth */
      duration: 1,
      precoder_granularity: "sameAsREG_bundle",
      css: {
        n_candidates: [ 0, 0, 4, 0, 0 ],
      },
      rar_al_index: 2,
      si_al_index: 2,

      uss: {
        n_candidates: [ 0, 4, 0, 0, 0 ],
        dci_0_1_and_1_1: true,
      },
      al_index: 1,
    },

    pdsch: {
      mapping_type: "typeA",
      start_symb: 1,
      n_symb: 13,
      dmrs_add_pos: 1,
      dmrs_type: 1,
      dmrs_max_len: 1,
      /* k0 delay in slots from DCI to PDSCH: automatic setting */
      /* k1 delay in slots from PDSCH to PUCCH/PUSCH ACK/NACK: automatic setting */
      mcs_table: "qam256",
      rar_mcs: 2,
      si_mcs: 6,
      /* If defined, force the PDSCH MCS for all UEs. Otherwise it is computed
       * based on DL channel quality estimation */
      /* mcs: 24, */
    },

    csi_rs: {
      nzp_csi_rs_resource: [
        {
          csi_rs_id: 0,
#if N_ANTENNA_DL == 1
          n_ports: 1,
          frequency_domain_allocation: "row2",
          bitmap: "100000000000",
          cdm_type: "no_cdm",
#elif N_ANTENNA_DL == 2
          n_ports: 2,
          frequency_domain_allocation: "other",
          bitmap: "100000",
          cdm_type: "fd_cdm2",
#elif N_ANTENNA_DL == 4
          n_ports: 4,
          frequency_domain_allocation: "row4",
          bitmap: "100",
          cdm_type: "fd_cdm2",
#elif N_ANTENNA_DL == 8
          n_ports: 8,
          frequency_domain_allocation: "other",
          bitmap: "110011",
          cdm_type: "fd_cdm2",
#else
#error unsupported number of DL antennas
#endif
          density: 1,
          first_symb: 4,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          power_control_offset: 0, /* dB */
          power_control_offset_ss: 0, /* dB */
          period: 80,
          offset: 1, /* != 0 to avoid collision with SSB */
          qcl_info_periodic_csi_rs: 0,
        },
#define USE_TRS        
#ifdef USE_TRS
        /* TRS : period of 40 ms, slots 1 & 2, symbols 4 and 8 */
        {
          csi_rs_id: 1,
          n_ports: 1,
          frequency_domain_allocation: "row1",
          bitmap: "0001",
          cdm_type: "no_cdm",
          density: 3,
          first_symb: 4,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          power_control_offset: 0, /* dB */
          power_control_offset_ss: 0, /* dB */
          period: 40,
          offset: 11,
          qcl_info_periodic_csi_rs: 0,
        },
        {
          csi_rs_id: 2,
          n_ports: 1,
          frequency_domain_allocation: "row1",
          bitmap: "0001",
          cdm_type: "no_cdm",
          density: 3,
          first_symb: 8,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          power_control_offset: 0, /* dB */
          power_control_offset_ss: 0, /* dB */
          period: 40,
          offset: 11,
          qcl_info_periodic_csi_rs: 0,
        },
        {
          csi_rs_id: 3,
          n_ports: 1,
          frequency_domain_allocation: "row1",
          bitmap: "0001",
          cdm_type: "no_cdm",
          density: 3,
          first_symb: 4,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          power_control_offset: 0, /* dB */
          power_control_offset_ss: 0, /* dB */
          period: 40,
          offset: 12,
          qcl_info_periodic_csi_rs: 0,
        },
        {
          csi_rs_id: 4,
          n_ports: 1,
          frequency_domain_allocation: "row1",
          bitmap: "0001",
          cdm_type: "no_cdm",
          density: 3,
          first_symb: 8,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          power_control_offset: 0, /* dB */
          power_control_offset_ss: 0, /* dB */
          period: 40,
          offset: 12,
          qcl_info_periodic_csi_rs: 0,
        },
#endif
      ],
      nzp_csi_rs_resource_set: [
        {
          csi_rs_set_id: 0,
          nzp_csi_rs_resources: [ 0 ],
          repetition: false,
        },
#ifdef USE_TRS
        {
          csi_rs_set_id: 1,
          nzp_csi_rs_resources: [ 1, 2, 3, 4 ],
          repetition: false,
          trs_info: true,
        },
#endif
      ],
      
     csi_im_resource: [
        {
          csi_im_id: 0,
          pattern: 1,
          subcarrier_location: 8,
          symbol_location: 8,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          period: 80,
          offset: 1, /* != 0 to avoid collision with SSB */
        },
      ],
      csi_im_resource_set: [
        {
          csi_im_set_id: 0,
          csi_im_resources: [ 0 ],
        }
      ],
      /* ZP CSI-RS to set the CSI-IM REs to zero */
      zp_csi_rs_resource: [
        {
          csi_rs_id: 0,
          frequency_domain_allocation: "row4",
          bitmap: "100",
          n_ports: 4,
          cdm_type: "fd_cdm2",
          first_symb: 8,
          density: 1,
          rb_start: 0,
          l_crb: -1, /* -1 means from rb_start to the end of the bandwidth */
          period: 80,
          offset: 1,
        },
      ],
      p_zp_csi_rs_resource_set: [
        {
          zp_csi_rs_resources: [ 0 ],
        },
      ],

      csi_resource_config: [
        {
          csi_rsc_config_id: 0,
          nzp_csi_rs_resource_set_list: [ 0 ],
          resource_type: "periodic",
        },
        {
          csi_rsc_config_id: 1,
          csi_im_resource_set_list: [ 0 ],
          resource_type: "periodic",
        },
#ifdef USE_TRS
        {
          csi_rsc_config_id: 2,
          nzp_csi_rs_resource_set_list: [ 1 ],
          resource_type: "periodic",
        },
#endif
      ],
      csi_report_config: [
        {
          resources_for_channel_measurement: 0,
          csi_im_resources_for_interference: 1,
          report_config_type: "periodic",
          period: 80,
          report_quantity: "CRI_RI_PMI_CQI",
#if N_ANTENNA_DL > 1    
          codebook_config: {
            codebook_type: "type1",
            sub_type: "typeI_SinglePanel",
#if N_ANTENNA_DL == 2
#elif N_ANTENNA_DL == 4
            n1: 2,
            n2: 1,
            codebook_mode: 1,
#elif N_ANTENNA_DL == 8
            n1: 4,
            n2: 1,
            codebook_mode: 1,
#endif
          },
#endif
          cqi_table: 2,
          subband_size: "value1",
        },
      ],
    },
    
    pucch: {
      pucch_group_hopping: "neither",
      hopping_id: -1, /* -1 = n_cell_id */
      p0_nominal: -90,
#if 0
        pucch0: {
          initial_cyclic_shift: 1,
          n_symb: 1,
        },
#else
        pucch1: {
          n_cs: 3,
          n_occ: 3,
          freq_hopping: true,
        },
#endif
#if NR_LONG_PUCCH_FORMAT == 2
        pucch2: {
          n_symb: 2,
          n_prb: 1,
          freq_hopping: true,
          simultaneous_harq_ack_csi: false,
          max_code_rate: 0.25,
        },
#elif NR_LONG_PUCCH_FORMAT == 3
        pucch3: {
          bpsk: false,
          additional_dmrs: false,
          freq_hopping: true,
          n_prb: 1,
          simultaneous_harq_ack_csi: true,
          max_code_rate: 0.25,
        },
#elif NR_LONG_PUCCH_FORMAT == 4
        pucch4: {
          occ_len: 4,
          bpsk: false,
          additional_dmrs: false,
          freq_hopping: true,
          simultaneous_harq_ack_csi: true,
          max_code_rate: 0.25,
        },
#endif
    },

    pusch: {
      mapping_type: "typeA",
      n_symb: 14,
      dmrs_add_pos: 1,
      dmrs_type: 1,
      dmrs_max_len: 1,
      tf_precoding: false,
      mcs_table: "qam256", /* without transform precoding */
      mcs_table_tp: "qam256", /* with transform precoding */
      ldpc_max_its: 5,
      /* k2, msg3_k2 delay in slots from DCI to PUSCH: automatic setting */
      p0_nominal_with_grant: -84,
      msg3_mcs: 4,
      msg3_delta_power: 0, /* in dB */
      beta_offset_ack_index: 9,

      /* hardcoded scheduling parameters */
      n_dmrs_cdm_groups: 1,
      n_layer: 1,
      /* if defined, force the PUSCH MCS for all UEs. Otherwise it is
       computed from the last received PUSCH. */
      /* mcs: 16, */
    },

    /* MAC configuration */
    mac_config: {
      msg3_max_harq_tx: 5,
      ul_max_harq_tx: 5, /* max number of HARQ transmissions for uplink */
      dl_max_harq_tx: 5, /* max number of HARQ transmissions for downlink */
      ul_max_consecutive_retx: 30, /* disconnect UE if reached */
      dl_max_consecutive_retx: 30, /* disconnect UE if reached */
      periodic_bsr_timer: 20,
      retx_bsr_timer: 320,
      periodic_phr_timer: 500,
      prohibit_phr_timer: 200,
      phr_tx_power_factor_change: "dB3",
      sr_prohibit_timer: 0, /* in ms, 0 to disable the timer */
      sr_trans_max: 64,
    },

    cipher_algo_pref: [],
    integ_algo_pref: [2, 1],

    inactivity_timer: 10000,

    drb_config: "drb_nr.cfg",
  },
}