NR SA CORESET0
The purpose of this tutorial is Not about creating any specific test cases. This is more about information sharing on how CORESET0 in NR SA is configured automatically by gNB software and how you can configure it manually when you want. SSB positioning and selecting an appropriate CORESET0 resource is one of the most complicated and confusing process in NR protocol, but Amari gNB specifies SSB and corresponding CORESET0 automatically. Of course, you can specify it manually as you like if you want any specific configuration. This tutorial will show you how you can figure out the automatically set configuration and how you can manually change the configuration if you need.
It is assumed that you already have basic understandings on what is the CORESET (If you are not familiar with the concept of the coreset itself, I would suggest to check out this note). CORESET0 is a specially designed coreset only SIB1 scheduling. The details of this CORESET (i.e, SIB1 scheduling information) cannot be broadcasted to UE). Why not ? Except MIB(PBCH), SIB1 is the first broadcast message, so there should be some other mechanism to provide the details of SIB1 sheduling to UE. The technique that 3GPP adopted for this is as follows.
- i) define various predefined set of configuration in 3GPP specification (both gNB and UE should have these predefined table in it)
- ii) Inform the UE on which table and which index of the table to use via MIB (PBCH)
The summary of this mechanism would be illustrated as below (as per my understanding).
Image Source : SIB1 decoding Procedure in Sharetechnote
In 3GPP, SSB SCS,PDCCH SCS, Min BW determines which table to apply and the MIB parameter determines the index of the selected table. In Amarisoft gNB, SSB SCS,PDCCH SCS, Min BW determines which table to apply and the index of the table is specified in enb.cfg. (The index specified in the configuration file is populated in MIB).
Table of Contents
- NR SA CORESET0
If you don't specify SSB and CORESET0 configuration manually, those are set automatically by Amari gNB. Most of the sample configurations that are installed by the installation package uses the automatic configuration (meaning that those configurations are not set explicitely in the configuration file). Followings are some of the examples showing the result of automatic configuration. You can check the specified SSB and coreset0 resource allocation from the gnb log file as shown below. (
Example 1 > CBW 20 Mhz
In this example, bandwith is configured to be 20Mhz and subcarrier spacing is configured to be 30Khz. Based on this, ssb_arfcn, k_ssb, ssb_prb, coreset0_prb (position of coreset0) and coreset0_idx are all automatically set by LTE software and printed in the logfile as metat data. (
Example 2 > CBW 40 Mhz
In this example, bandwith is configured to be 40Mhz and subcarrier spacing is configured to be 30Khz. Based on this, ssb_arfcn, k_ssb, ssb_prb, coreset0_prb (position of coreset0) and coreset0_idx are all automatically set by LTE software and printed in the logfile as metat data. (
Example 3 > CBW 10 Mhz
In this example, bandwith is configured to be 10Mhz and subcarrier spacing is configured to be 30Khz. Based on this, ssb_arfcn, k_ssb, ssb_prb, coreset0_prb (position of coreset0) and coreset0_idx are all automatically set by LTE software and printed in the logfile as metat data. (
Common Errors for CORESET Resource Allocation
Followings are some of the common misconfigurations causing CORESET0 related errors. (NOTE : This is not the exhaustive list of misconfigurations. These are only examples of common misconfiguration and you may come across various other cases as well). In the examples shown below, I intentionally set the configuration to cause errors, but you can use the same parameter to fix the coreset related errors.
Example 1 > Offset too big
This is the case where coreset 0 bandwidth is narrower than the CBW (channel bandwidth), but the coreset 0 boundary gets out of CBW due to too large offset value
Example 2 > Frequency Span too wide
This is the case where the coreset 0 bandwidthis wider than the configured channel bandwidth. This case can be interpreted as follows :
- The number of RB of the configured coreset 0(n_rb_coreset0) is larger than the max number of RB for the configured channel bandwidth (You can check out the max number of RB for each channel bandwidth and subcarrier spacing in this note)
- For example, you cannot allocate coreset 0 with the NRB(number of RB) of 48 for the channel bandwidth with the max NRB of smaller than 48 (e.g, CBW 5Mhz with SCS 15Khz or CBW 10Mhz with SCS 30Khz).
RRC / NAS Signaling
: Amarisoft Callbox does not print out the full contents of MIB (PBCH) in the trace log (The MIB contents related to CORESET 0 is printed in the log at meta data section as shown above). The ASN.1 structure of NR SA MIB is as shown below.